The invention relates to a switching power supply device and switching power supply control circuit comprising a series resonance circuit having a current resonance inductor and a current resonance capacitor, and in particular relates to a switching power supply device and switching power supply control circuit which eliminated backflow of current under light loading.
Switching power supply devices comprising current resonance-type converters such as that shown in FIG. 7 are known as switching power supply devices of the prior art. In such current resonance converters, an input DC voltage Vi is applied to a series resonance circuit having a resonance inductor Lr and a resonance capacitor Cr, and two main switching elements Qa, Qb, comprising MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) or similar, are turned on and off to control the path of the primary-side current flowing in the primary windings L1 of a power conversion transformer T, so that a sinusoidal current flows in the primary windings L1 of the transformer T. The secondary windings L2 and tertiary windings L3 of the transformer T (where the windings ratio L1:L2:L3 is taken to be n:1:1) are connected to rectifying diodes D1, D2 which rectify the respectively induced secondary currents I1, I2, and to an output capacitor CO which smoothes the output voltage VO to the load LD. Further, the output voltage VO to the load LD is fed back to a driving circuit 3 to turn on and off the main switching elements Qa, Qb via an error amplifier 1 and a VCO (Voltage Controlled Oscillator) 2, and the current flowing in the primary windings L1 of the transformer T and the voltage are controlled to control the output voltage VO at a constant voltage. The VCO 2 functions such that, from the output of the error amplifier 1, when the output voltage VO is judged to be higher than a preset voltage or the loading is light, the output frequency is raised, and when the output voltage VO is judged to be lower than a preset voltage or the loading is heavy, the output frequency is lowered.
However, when using such a switching power supply device as a low-voltage, large-current power supply, when secondary currents I1 and I2 flow in the rectifying diodes D1 and D2 provided on the secondary side of the transformer T, large current losses VF×IO due to the forward-direction voltage drop VF across the rectifying diodes D1, D2 occur. This current IO represents the current values of either of the secondary currents I1, I2.
Hence a separate-excitation driving type current resonance circuit is used, in which MOSFETs Qs1, Qs2 with low on-state resistances are connected as switching elements for synchronous rectification as shown in FIG. 8 in place of these rectifying diodes D1, D2 to perform synchronous rectification, to reduce such power losses. The MOSFETs Qs1, Qs2 in FIG. 8 are controlled by the driving circuit 3 to be turned on and off synchronously with the operating frequency fop at which the primary-side main switching elements Qa, Qb are turned on and off, and the secondary currents I1, I2 are stored in the capacitor CO in alternation.
Here, separate-excitation synchronous rectification in the current resonance converter of FIG. 8, in which the secondary-side rectifying diodes D1, D2 in FIG. 7 are replaced with MOSFETs Qs1, QS2 with low on-state resistances, is considered.
Synchronous rectification methods include self-excitation driving methods and separate-excitation driving methods. In separate-excitation driving methods, driving signals are output by a logic circuit, and if the logic circuit is incorporated in a power supply IC (Integrated Circuit), synchronous rectification functions can easily be realized by the power supply manufacturer. Hence IC manufacturers have proposed various separate-excitation driving methods (see U.S. Pat. No. 7,184,280, U.S. Patent Application No. 2008/0055942, U.S. Patent Application No. 2005/0122753, Japanese Patent Application Laid-open No. 2005-198438, and Japanese Patent Application Laid-open No. 2005-198375, described below).
Such a switching power supply device of the prior art is configured so as to cause the main switching elements Qa, Qb to perform switching operation, to obtain an arbitrary DC output via the voltage-conversion transformer T. In such a device, charge accumulated on the capacitor CO is discharged, according to the magnitude and similar of the load LD connected to the secondary side, so that current flowing back to the transformer T (back current) occurs, and the problem of power loss in the backflow region arises.
Simply considering separate-excitation driving synchronous rectification, it is thought to be sufficient that the synchronous driving signals of the MOSFETs Qs1, Qs2 are synchronized with the gate signals controlling switching of the main switching elements Qa, Qb. But in actuality, if backflow regions are not detected in each of the operating modes, and the signals are not converted into driving signals synchronized therewith, charge accumulated on the output capacitor CO is discharged, a current flowing back to the transformer T (back current) occurs, and efficiency is reduced. Further, there is the concern of circuit destruction due to the backflow of power to the primary side of the transformer T.
In the current resonance converter of FIG. 8, the transformer T of the current resonance converter of FIG. 7 is shown separated into an excited inductance component Lm and an ideal transformer Ti, and the operating principle is presented so as to facilitate understanding. Here, prior to explaining power losses in the above-described backflow region, the principle of operation of a current resonance converter is explained.
For the current resonance converter shown here, two types of basic current resonance frequencies, fr1 and fr2, are defined, as in equations (1) and (2) below. Here Lr, Lm and Cr are respectively the inductance of the resonance inductor Lr, the excitation inductance component of the transformer T, and the capacitance of the resonance capacitor Cr.
                              fr          ⁢                                          ⁢          1                =                  1                      2            ⁢            π            ⁢                                          Lr                ·                Cr                                                                        (        1        )                                          fr          ⁢                                          ⁢          2                =                  1                      2            ⁢            π            ⁢                                                            (                                      Lr                    +                    Lm                                    )                                ·                Cr                                                                        (        2        )            
In the switching power supply device of FIG. 8, when power is supplied to the load LD the voltage across the excitation inductance component Lm of the transformer T is clamped at n×(VO+VF) according to the output voltage VO, the excitation inductance component Lm does not contribute to current resonance, and through operation at the first resonance frequency fr1 (see equation (1) above) determined by the resonance capacitor Cr and resonance inductor Lr, power is supplied to the secondary-side circuit. In this case, the sum of the current Im flowing in the excitation inductance component Lm and the resonance current Ir flows to the resonance capacitor Cr as a charge/discharge current. At this time, the operation frequency fop of the main switching elements Qa, Qb is controlled by the VCO 2 so as to stabilize the output voltage VO.
The second resonance frequency fr2 (see equation (2) above) is the resonance frequency when power is not supplied to the load LD connected to the secondary side of the transformer T; the ideal transformer Ti does not function as a transformer, and the voltage across the excitation inductance component Lm of the transformer T is not clamped, so that resonance operation occurs mainly due to the capacitance Cr of the resonance capacitor Cr, the resonance inductance Lr of the resonance inductor Lr, and the excitation inductance component Lm.
The specific resonance operation of the current resonance converter can be considered by dividing operation into six operation modes (Mode 1 to Mode 6), as shown in FIG. 9, according to the relation between the operation frequency fop and the first resonance frequency fr1 (hereafter simply called the resonance frequency), and the magnitude of the load LD connected to the secondary side of the transformer T.
That is, in FIG. 9, Mode 1 to Mode 3 are for cases in which the operating frequency fop is lower than the resonance frequency fr1, and Mode 4 to Mode 6 are for cases in which the operating frequency fop is equal to or higher than the resonance frequency fr1. If the magnitude of the connected load LD is greater than 50% of the rated load (maximum load) for the switching power supply device, the state is a heavy load (HL) state; if the load magnitude is 20 to 50%, the state is a light load (LL) state; and if the load is less than 20%, the state is a very light load (VLL) state.
Secondary-side current waveforms induced via the transformer T in each of the operation modes will be explained, using FIG. 10 to FIG. 15. Here, the backflow region in each operation mode is determined by the relation between the operating frequency fop and the resonance frequency fr1 of the current resonance converter, and by the load LD. The operating frequency fop changes with the circuit parameters and the load state, but the resonance frequency fr1 is determined by the magnitudes of the resonance capacitor Cr and the resonance inductor Lr. Hence while synchronous rectification in which the synchronous driving signals Vgs1, Vgs2 are completely synchronized with the power switching signals as shown in FIG. 8 is a simple method, in this case the five backflow regions described below pose problems, and measures to resolve these problems are necessary.
That is, in the first operating mode (Mode 1) shown in FIG. 10 of a switching power supply device which turns two main switching elements Qa, Qb on and off by means of respective gate signals Vga, Vgb to supply secondary currents I1, I2, in the second half of each half-period (Top/2) of switching operation, if the MOSFETs Qs1, Qs2 for synchronous rectification are not reliably turned off, backflow of the secondary currents I1, I2 cannot be impeded. This is because the relation between the operating frequency fop and the resonance frequency fr1 in the first operating mode is fop<fr1, so that even if a half-period of resonance operation (Tr/2) ends, a half-period (Top/2) of switching operation has not yet ended. Hence when the gate signals Vga, Vgb shown in FIGS. 10A and 10B are output without modification as synchronous driving signals Vgs1, Vgs2 to the synchronous rectification MOSFETs Qs1, Qs2 shown in FIG. 8, a backflow current flows in this timing region (range A).
In the case of the second operating mode (Mode 2), in which the operating frequency fop is lower than the resonance frequency fr1, and moreover the load LD is in the light load (LL) state, separately from range A in which backflow occurs in FIG. 10, there is the concern that backflow may occur in range B shown in FIG. 11 as well (the region of the timing immediately after the main switching element Qa or Qb is turned on). This is because in a current resonance converter, when the load LD is somewhat lighter, the timing of the start of resonance operation lags behind the start of switching operation. And, operation is such that when the load LD becomes still lighter, the timing of the start of resonance operation also lags further.
Similarly, in the case of the third operating mode (Mode 3), in which the operating frequency fop is lower than the resonance frequency fr1, and moreover the load LD is in the very light loading (VLL) state with a still-smaller load, backflow occurs in range A and in range B. And, within half of the resonance period Tr shown in FIG. 12, backflow also occurs in range C, equivalent to a range in which resonance has ended.
In the fourth operating mode (Mode 4), shown in FIG. 13, the operating frequency fop is equal to or greater than the resonance frequency fr1, and moreover the load LD is in the heavy loading (HL) state; in this case, the secondary currents I1, I2 are continuous, and so there is no concern of the occurrence of backflow.
In the fifth operating mode (Mode 5), shown in FIG. 14, the operating frequency fop is equal to or greater than the resonance frequency fr1, and moreover the load LD is in the light loading (LL) state; backflow occurs in range D (the region of the timing immediately after a main switching element Qa or Qb is turned on).
In the case of the sixth operating mode (Mode 6), in which the operating frequency fop is equal to or greater than the resonance frequency fr1, and moreover the state is the very light loading (VLL) state, backflow occurs in range D shown in FIG. 15. And, in the region of range E, in the interval in which the two main switching elements Qa, Qb are each turned on, backflow also occurs with the timing of the supply of power to the secondary side. This is because in the very light loading (VLL) state, little energy is sent to the secondary side, and so resonance operation ends in a short length of time. Hence when applying a signal (the same signal) synchronized with the gate signals Vga, Vgb to the synchronous rectification MOSFETs Qs1, Qs2 as the synchronous driving signals Vgs1, Vgs2, backflow occurs in each of the operating modes 1 to 3, 5 and 6, and so it has been necessary to shape signal waveforms for the synchronous driving signals Vgs1, Vgs2 in each of the corresponding regions (ranges A to E).
Hence in a conventional switching power supply device, a CWP (Constant Width Pulse) generation circuit is provided which outputs a constant-width pulse (CWP) signal with a pulse width slightly narrower than the turn-on intervals of the gate signals Vga, Vgb, to shape the waveforms of the synchronous driving signals Vgs1, Vgs2 for the synchronous rectification MOSFETs (see for example U.S. Pat. No. 7,184,280). That is, when the operating frequency fop is the same as or higher than the resonance frequency fr1, the synchronous driving signals Vgs1, Vgs2 are synchronized with the gate signals Vga, Vgb, and when the operating frequency fop is lower than the resonance frequency fr1, the synchronous driving signals Vgs1, Vgs2 are made to end in synchronization with the constant-width pulse signal CWP. By this means, even when MOSFETs Qs1, Qs2 with low on-state resistances are substituted for the secondary-side rectifying diodes D1, D2, back currents from the secondary side can be prevented.
However, in the invention disclosed in U.S. Pat. No. 7,184,280, the timing of the rising edge of the synchronous driving signals Vgs1, Vgs2 is always synchronized with the gate signals Vga, Vgb, so that it is difficult to prevent backflow immediately before the beginning of the secondary current, as in the backflow region (range B) in the second operation mode (Mode 2). Also, in Mode 4 to Mode 6, when the operating frequency fop is the same as or higher than the resonance frequency fr1, if the synchronous driving signals Vgs1, Vgs2 are synchronized with the gate signals Vga, Vgb, then backflow in the light loading (LL) state and in the very light loading (VLL) state can be prevented.
As another switching power supply device, a method is conceivable in which a control circuit of synchronous rectification MOSFETs is configured, as shown in FIG. 16A (see for example U.S. Patent Application No. 2008/0055942). Operation waveforms of the various portions are shown in FIG. 16B.
In this method, the drain-source voltage (Vds (on)) of a synchronous rectification switching element (MOSFET) is compared with a reference voltage REF by a comparator 510 to detect whether the synchronous rectification MOSFET, or its body diode, is conducting; when conduction is detected, and moreover during the interval in which the gate signal Vgp is H (high), a signal to turn on the synchronous rectification MOSFET is applied to the synchronous rectification MOSFET. That is, an AND (logical product) circuit 430 generates the AND signal of the comparison signal Vdsc which is the output of the comparator 510 and the gate signal Vgp of the primary-side main switching elements Qa, Qb, and outputs this signal, as the waveform-shaped synchronous driving signal Vgs (that is, Vgs1 and Vgs2), to the synchronous rectification MOSFETs Qs1, Qs2 which are the switching elements.
In general, the drain-source voltage Vds of a MOSFET is equal to the forward-direction voltage drop VF across the body diode in the state in which the MOSFET is turned off and current is flowing in the body diode. The forward-direction voltage drop VF across the body diode is precisely −VF, taking the source potential as reference. On the other hand, when the MOSFET is in the on state, the voltage is the product of the on-state resistance and the flowing current, and the value (absolute value) is normally lower than VF. The above-described reference voltage REF is set to be substantially lower than this absolute value, in order that current flowing in the body diode can initially be detected and MOSFET turn-on can be allowed, and then, after the MOSFET has been turned on, the MOSFET can be continually turned on even when the drain-source voltage Vds becomes low. In actuality, in consideration of noise and similar, the value must be made high enough that the fact that the MOSFET or the body diode thereof is conducting can be detected without error.
However, as shown in FIG. 16B, when the secondary current Is decreases and becomes zero, no matter how low the value of the reference voltage REF, the production of the MOSFET on-state resistance and the flowing current will at some time become smaller. Then, the comparison signal Vdsc is inverted, the MOSFET is turned off, and a state ensues in which current flows in the body diode, so that the drain-source voltage Vds becomes −VF. By this mean the comparison signal Vdsc is again inverted, the MOSFET is again turned on, and as a result the comparison signal Vdsc is inverted yet again. Thereafter, as indicated by the error region in FIG. 16B, MOSFET on-off switching is repeated at high frequency until the secondary current Is completely reaches zero. This oscillation phenomenon is more marked when the load is light and the secondary current Is declines. In this way, in the invention described in U.S. Patent Application No. 2008/0055942, high-frequency oscillation is repeated each time the secondary current Is decreases to reach zero, and so this method poses problems from the standpoints of noise and power conversion efficiency.
U.S. Patent Application No. 2005/0122753 describes an invention in which the turn-on threshold value (VTH2) is set taking into account the conduction voltage of the body diode (internal diode). Here, the turn-on timing of the synchronous driving signal is determined solely in terms of the conduction voltage of the internal diode, and so there is the problem that erroneous operation readily occurs due to the dead times set for the gate signals Vga, Vgb on the primary side. And, because the threshold value determining the turn-off timing (VTH1) is an extremely small and negative value of approximately −20 mV, there are the problems that operation is easily affected by noise, and that the timing of the turn-off operation is unstable.
In another switching power supply device, the primary-side resonance current is detected by a current transformer, the excitation current is detected by secondary-side auxiliary windings, and the resonance current detection signal is compared with the excitation current detection signal. A synchronous rectification signal is generated based on a signal detecting whether the comparison result signal, the power switching signal, and the resonance current detection signal exceed 0 A (see for example Japanese Patent Application Laid-open No. 2005-198438).
By means of the technology of Japanese Patent Application Laid-open No. 2005-198438, the problem of backflow can be resolved for each of the discontinuous modes, but in operating modes with heavy load states (Modes 1 and 4), the synchronous rectification MOSFET turn-on timing lags, so that power efficiency is reduced. Moreover, a current transformer and auxiliary windings are used in the detection circuit, so that the circuit configuration is more complex, and designing the device with optimal adjusted values is difficult, so that this method is undesirable from the standpoint of cost as well.
Further, the invention disclosed in Japanese Patent Application Laid-open No. 2005-198375 relates to a synchronous rectification circuit which can prevent the flowing of current in the reverse direction, and a power converter with reduced power conversion losses. The source-drain voltage of a synchronous rectification transistor is compared by a comparator circuit, and when reverse-direction current is detected, current flow is prevented by switching means. Here, the timing with which the synchronous rectification transistor is turned off is determined, but there is no description of the turn-on timing. Hence this invention is not effective as a means of preventing backflow of current (ranges B and D) in the above-described second operating mode (Mode 2), third operating mode (Mode 3), fifth operating mode (Mode 5), and sixth operating mode (Mode 6).
Thus there have been no switching power supply devices of the prior art comprising driving circuits so as to reliably prevent backflow of secondary current to the primary side in all of the above-described six operating modes (see FIG. 9). In particular, a method of constantly detecting the loading state, and of causing a synchronous rectification MOSFET not to be turned on when in a very light loading state, has been effective for addressing current backflow (ranges C and E) in the third operating mode (Mode 3) and sixth operating mode (Mode 6). However, such methods of detecting a light loading state have the following problems.
One such method entails monitoring the output signal of an error amplifier 1, and detecting the state of the load connected to the switching power supply device. However, in this detection method, the load state is not detected on a pulse-by-pulse basis (here “pulse” means a switching pulse); that is, the load state is not detected each time switching is performed. And, because the error amplifier 1 itself has a response delay, a time delay necessarily occurs from the time a very light loading state is entered until a state detection signal indicating a very light load is output, so that switching operation of the synchronous rectification MOSFET cannot be stopped immediately, and a fundamental resolution of the problem of backflow is not obtained. Further, in ordinary current resonance converters, the VCO (voltage controlled oscillator) 2 is designed so as to reduce frequency fluctuations caused by load fluctuations. Hence fluctuations in error signals from the error amplifier 1 are also small, load fluctuations cannot easily be detected reliably, and moreover such detection is easily affected by noise.
As another method, it is also possible to use a resistance to monitor the current flowing in the load and detect a light loading state. However, power consumption occurs in the resistance provided on the secondary side, and so there is the problem that lowering of the power efficiency is unavoidable.